1 www.pericom.com p-0.1 04/29/11 all trademarks are property of their respective owners. pi6c557-03a block diagram phase l ock lo o p cr ystal driver vd d gnd x1/c l k x 2 25 m hz c ry s tal or c l oc k cont rol logic s s 1 : s s 0 2 s 1: s 0 2 c l k 0 c l k 0 r r c l k 1 c l k 1 2 2 o e pulling c a pacitor s pin configuration (16-pin tssop) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vddx clk0 clk0 gnda vdda clk1 clk1 iref s0 s1 ss0 x1/clk x2 oe gndx ss1 description te pi6c557-03a is a spread spectrum clock generator compli - ant to pci express? 2.0 and ethernet requirements. te device is used for pc or embedded systems to substantially reduce electro - magnetic interference (emi). te pi6c557-03a provides two diferential (hcsl) or lvds spread spectrum outputs. te pi6c557-03a is confgured to se - lect spread and clock selection. using pericom's patented phase- locked loop (pll) techniques, the device takes a 25mhz crystal input and produces two pairs of diferential outputs (hcsl) at 25mhz, 100mhz, 125mhz and 200mhz clock frequencies. it also provides spread selection of -0.5%, -0.75%, and no spread. features ? pcie? 2.0 compliant phase jitter - 2.1ps rms (typ) ? lvds compatible outputs ? supply voltage of 3.3v 10% ? 25mhz crystal or clock input frequency ? hcsl outputs, 0.8v current mode diferential pair ? jitter 35ps cycle-to-cycle (typ) ? spread of -0.5%, -0.75%, and no spread ? industrial temperature range ? spread bypass option available ? spread and frequency selection via external pins ? packaging: (pb-free and green) 16-pin tssop (l16) 16-pin qsop (q16) pcie 2.0 clock generator with 2 hcsl outputs 11-0061
2 www.pericom.com p-0.1 04/29/11 all trademarks are property of their respective owners. pi6c557-03a pcie 2.0 clock generator with 2 hcsl outputs pin description pin # pin name i/o type description 1 s0 input select pin 0 (internal pull-up resistor). see table 1. 2 s1 input select pin 1 (internal pull-up resistor). see table 1. 3 ss0 input spread select pin 0 (internal pull-up resistor). see table 2. 4 x1/clk input crystal or clock input. connect to a 25mhz crystal or single ended clock. 5 x2 output crystal connection. leave unconnected for clock input. 6 oe input output enable. internal pull-up resistor. 7 gndx power crystal ground pin. 8 ss1 input spread select pin 1 (internal pull-up resistor). see table 2. 9 iref output precision resistor attached to this pin is connected to the internal current reference. 10 clk1 output hcsl compliment clock output 11 clk1 output hcsl clock output 12 vdda power connect to a +3.3v source. 13 gnda power output and analog circuit ground. 14 clk0 output hcsl compliment clock output 15 clk0 output hcsl clock output 16 vddx power connect to a +3.3v source. table 1: output select table s1 s0 clk(mhz) 0 0 25 0 1 100 1 0 125 1 1 200 table 2: spread selection table ss1 ss0 spread 0 0 no spread 0 1 down -0.5 1 0 down -0.75 1 1 no spread 11-0061
3 www.pericom.com p-0.1 04/29/11 all trademarks are property of their respective owners. pi6c557-03a pcie 2.0 clock generator with 2 hcsl outputs application information decoupling capacitors decoupling capacitors of 0.01f should be connected between each v dd pin and the ground plane and placed as close to the v dd pin as possible. crystal use a 25mhz fundamental mode parallel resonant crystal with less than 300ppm of error across temperature. crystal capacitors c l = crystals's load capacitance in pf crystal capacitors (pf) = (c l - 8) *2 for example, for a crystal with 16pf load caps, the external ef - fective crystal cap would be 16 pf. (16-8)*2=16. current source (iref) reference resistor - r r if board target trace impedance is 50?, then r r = 475? providing an iref of 2.32 ma. te output cur - rent (i oh ) is 6*iref. output termination te pci express diferential clock outputs of the pi6c557-03a are open source drivers and require an external series resistor and a resistor to ground. tese resistor values and their allow - able locations are shown in detail in the pci express layout guidelines section. te pi6c557-03a can be confgured for lvds compatible volt - age levels. see the lvds compatible layout guidelines section. output structures r r = 47 5 6 * i r e f = 2 . 3 m a i r e f s ee o u t pu t t e r m i na t i o n se c t i on s ? 11-0061
4 www.pericom.com p-0.1 04/29/11 all trademarks are property of their respective owners. pi6c557-03a pcie 2.0 clock generator with 2 hcsl outputs typical pci express (hcsl) waveform 0 . 175 v 0. 5 2 v 0 . 175 v 0. 5 2 v t o r t o f 250 p s 4 0 0 p s 8 0 0 m v 0 pci express device routing r s r s r t r t pc i -ex press l o a d o r c o n n e c t o r l1 l 2 l 3? l4 l1 ? l2 ? l3 l 4? pi6c 5 5 7 -0 3 o u t pu t c l oc k pci express layout guidelines common recommendations for diferential routing dimension or value unit l1 length, route as non-coupled 50? trace. 0.5 max inch l2 length, route as non-coupled 50? trace. 0.2 max inch l3 length, route as non-coupled 50? trace. 0.2 max inch r s 33 ? r t 49.9 ? diferential routing on a single pcb dimension or value unit l4 length, route as coupled microstrip 100? diferential trace. 2 min to 16 max inch l4 length, route as coupled stripline 100? diferential trace. 1.8 min to 14.4 max inch diferential routing to a pci express connector dimension or value unit l4 length, route as coupled microstrip 100? diferential trace. 0.25 min to 14 max inch l4 length, route as coupled stripline 100? diferential trace. 0.225 min to 12.6 max inch 11-0061
5 www.pericom.com p-0.1 04/29/11 all trademarks are property of their respective owners. pi6c557-03a pcie 2.0 clock generator with 2 hcsl outputs application information lvds recommendations for diferential routing dimension or value unit l1 length, route as non-coupled 50? trace. 0.5 max inch l2 length, route as non-coupled 50? trace. 0.2 max inch rp 100 ? rq 100 ? rt 150 ? l3 length, route as 100? diferential trace. l3 length, route as 100? diferential trace. lvds device routing l1 l2? l3 l1 ? l2 l3 ? r q r p lv d s d e v i c e l o a d pi6 c5 5 7- 0 3 c l oc k o u t pu t r t r t 11-0061
6 www.pericom.com p-0.1 04/29/11 all trademarks are property of their respective owners. pi6c557-03a pcie 2.0 clock generator with 2 hcsl outputs supply voltage to ground potential . . . . . . . . . . . . . . . . . . . . . . . 5.5v all inputs and outputs . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v ambient operating temperature . . . . . . . . . . . . . . . . . . -40 to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150c soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c eds protection (input) . . . . . . . . . . . . . . . . . . . . . 2000 v min (hbm) electrical specifications recommended operation conditions parameter min. typ. max. unit ambient operating temperature -40 +85 c power supply voltage (measured in respect to gnd) +3.0 +3.6 v dc characteristics (v dd = 3.3v 10%, t a = -40c to +85c) symbol parameter conditions min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ih input high voltage (1) oe 2.0 v dd +0.3 v v il input low voltage (1) oe gnd -0.3 0.8 v i il input leakage current 0 < vin < v dd with input pull-up and pull-downs -20 20 a without input pull-up and pull-downs -5 5 i dd operating supply cur - rent r l = 50, c l = 2pf 95 ma i ddoe oe = low 50 ma c in input capacitance @ 55mhz 7 pf c out output capacitance @ 55mhz 6 pf l pin pin inductance 5 nh r out output resistance clk outputs 3.0 k notes: 1. single edge is monotonic when transitioning through region. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) note: stresses greater than those listed under maxi - mum ratings may cause permanent damage to the device. tis is a stress rating only and func - tional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. expo - sure to absolute maximum rating conditions for extended periods may afect reliability. 11-0061
7 www.pericom.com p-0.1 04/29/11 all trademarks are property of their respective owners. pi6c557-03a pcie 2.0 clock generator with 2 hcsl outputs termal characteristics symbol parameter conditions min. typ. max. unit ja termal resistance junction to ambient still air 90 c/w jc termal resistance junction to case 24 c/w recomended crystal specifcation pericom recommends: a) gc2500003 xtal 49s/smd(4.0 mm), 25m, cl=18pf, +/-30ppm http://www.pericom.com/pdf/datasheets/se/gc_gf.pdf b) fy2500081, smd 5x3.2(4p), 25m, cl=18pf, +/-30ppm http://www.pericom.com/pdf/datasheets/se/fy_f9.pdf c) fl2500047, smd 3.2x2.5(4p), 25m, cl=18pf, +/-20ppm http://www.pericom.com/pdf/datasheets/se/fl.pdf hcsl output ac characteristics (v dd = 3.3v 10%, t a = -40c to +85c) symbol parameter conditions min. typ. max. unit f in input frequency 25 mhz v out output frequency 25 200 mhz v oh output high voltage (1,2) 100 mhz hcsl output @ v dd = 3.3v 660 800 900 mv v ol output low voltage (1,2) -150 0 mv v cpa crossing point voltage (1,2) absolute 250 350 550 mv v cn crossing point voltage (1,2,4) variation over all edges 140 mv j cc jitter, cycle-to-cycle (1,3) 35 60 ps j rms pcie rms jitter pcie 2.0 test method @ 100mhz output 3.1 ps mf modulation frequency spread spectrum 30 31.5 33 khz t or rise time (1,2) from 0.175v to 0.525v 175 500 ps t of fall time (1,2) from 0.525v to 0.175v 175 500 ps t skew skew between outputs at crossing point voltage 50 ps t duty-cycle duty cycle (1,3) 45 55 % t oe output enable time (5) all outputs 10 s t ot output disable time (5) all outputs 10 s t stable from power-up to v dd =3.3v from power-up v dd =3.3v 3.0 ms t spread setting period afer spread change setting period afer spread change 3.0 ms notes: 1. r l = 50-ohm with c l = 2 pf 2. single-ended waveform 3. differential waveform 4. measured at the crossing point 5. clk pins are tri-stated when oe is low 11-0061
8 www.pericom.com p-0.1 04/29/11 all trademarks are property of their respective owners. pi6c557-03a pcie 2.0 clock generator with 2 hcsl outputs packaging mechanical: 16-pin tssop (l) 1 description: 16-pin, 173-mil wid e , tssop p a cka ge code: l document contr ol no . pd - 1310 revision: e d a te: 03/09/05 note: 1. package outline exclusive of mold flash and metal burr 2. controlling dimentions in millimeters 3. ref: jedec mo-153f/ab pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com .193 .201 .047 max. .002 .006 seating plane .0256 bsc .018 .030 .004 .008 .252 bsc 1 16 .169 .177 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 1.20 4.9 5.1 0.65 0.19 0.30 .007 .012 note: for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 11-0061
9 www.pericom.com p-0.1 04/29/11 all trademarks are property of their respective owners. pi6c557-03a pcie 2.0 clock generator with 2 hcsl outputs packaging mechanical: 16-pin qsop (q) 1 .189 .197 .053 .069 .004 .010 seating plane .025 bsc .007 .010 .228 .244 1 16 .150 .157 x.xx x.xx denotes dimensions in millimeters 0.635 4.80 5.00 1.35 1.75 5.79 6.19 0.101 0.254 .008 .012 0.203 0.305 3.81 3.99 0.178 0.254 0.38 .008 0.203 .015 x 45 ref detail a detail a .008 0.20 min. guage plane .010 0.254 .041 1.04 ref .016 .035 0.41 0.89 0?-6? .008 .013 0.20 0.33 description: 16-pin 150-mil wide qsop p a cka ge code: q document contr ol no . pd - 1201 revision: g d a te: 11/07/07 note: 1) controlling dimensions in inche s . 2) ref: jedec mo-137b/ab. 3) dimensions do not include mold flash, protrusions or gate burrs pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com ordering information ordering code package code package type pic55-03ale l pb-free green, 1-pin tssop pic55-03ae pb-free green, 1-pin sop notes: ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging note: for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 11-0061
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